1. Field of the Invention
The present invention relates to an asynchronous semiconductor memory device like a flash memory, and, more particularly, to a semiconductor memory device which uses an internal voltage obtained by boosting the supply voltage.
2. Description of the Related Art
FIG. 6 illustrates a read circuit for an NOR type flash memory. A word line WL is connected to the output terminal of a word line driver 61, and the control gate of a memory cell MC constituted of an EEPROM (Electrically Erasable Programmable Read Only Memory) is connected to this word line WL. A power supply SW for the word line driver 61 is set to a high potential Vpp at the time of programming the EEPROM, and is set to Vcc when reading data therefrom. At the time of data reading, non-selected word lines are set to 0 V while the selected word line is set to Vcc. Of the selected cells, the cells from which data has been erased and whose threshold voltages are equal to or less than Vcc are turned on, so that data "1" is read out. Meanwhile, the cells in which data has been written and whose threshold voltages are equal to or greater than Vcc are turned off, allowing data "0" to be read out. Particularly, as the difference V.sub.M between the maximum value of the threshold value distribution and the supply voltage Vcc increases, a greater current can flow through the data-erased cells as shown in FIG. 7. This can improve the reading speed.
To reduce the consumed power of a microprocessor and the like, the supply voltage is recently apt to be reduced to 3.3 V.+-.0.3 V from 5 V.+-.0.5 V. To reduce the supply voltage in the circuit structure shown in FIG. 6 while ensuring the satisfactory performance, however, the distribution of the threshold voltage shown in FIG. 7 should be narrowed. As the distribution of the threshold voltage depends on a variation in the process, such as the shape of the memory cells or the impurity density, it is not easy to narrow the distribution of the threshold voltage. In this respect, word line driving systems as exemplified in FIGS. 8 and 9 have been proposed in place of the system in FIG. 6 which directly provide the supply voltage Vcc to the word lines.
The system shown in FIG. 8 drives the word lines, when selected, based on a boosted supply voltage Vcc, while the system in FIG. 9 uses as the internal supply voltage a boosted voltage Vint always produced from the supply voltage Vcc by a booster circuit 91.
In the circuit shown in FIG. 8, the potentials on word lines are boosted as follows. First, for the selected word line, a reset signal Reset and a boost signal Boot are set to a low level, and a select signal Sel is set to a high level. Then, the potential V.sub.WL of the word line WL is precharged to EQU V.sub.WL =Vcc-Vthn (1)
where Vthn is the threshold voltage of an N channel MOSFET. Thereafter, when the boost signal Boot is set to a high level, the potential V.sub.WL of the word line WL is boosted to EQU V.sub.WL =Vcc{1+(C.sub.WL /Cboot)}-Vthn (2)
where C.sub.WL is the capacitance of the word line and Cboot is the capacitance of the boosting capacitor. To change the word line from this state to the non-selected state, the select signal Sel should be set to a low level while setting the reset signal Reset to a high level.
To increase the potential V.sub.WL on the word line WL, this method requires the following condition as apparent from an equation (2). EQU Cboot&gt;&gt;C.sub.WL
That is, it is necessary to provide a boosting capacitor whose capacitance is equal to or greater than the capacitance of the word line. Even in the case where the capacitance of the word line is reduced by separating the memory cells into groups of memory cells, for example, a boosting capacitor having a capacitance greater by several factors than the capacitance of the word line should be formed in the chip, significantly increasing the occupying area in the chip.
In the circuit shown in FIG. 9, the voltage boosted by the booster circuit 91 is accumulated in a capacitor 92. Since the capacitance of this capacitor 92 need not be greater than the capacitance of the entire word lines, this circuit occupies a less area than the circuit shown in FIG. 8. As shown in FIG. 10, however, an asynchronous memory like the ordinary flash memory allows for a skew time Tskew or the unsettled time from the change in the first address signal A.sub.R0 to the change in the last address signal A.sub.Rn and to the settlement of the true select address signal. This means that the access time Tacc from the settlement of the last address signal A.sub.Rn to the point of data output should be determined regardless of the length of the skew time Tskew. It is however known that in the internal operation of the memory, some word line is always selected in the skew time Tskew and when the word line driver is constituted of a CMOS inverter, the through current flows at the time of the transition of the logic level. With the circuit structure shown in FIG. 9, therefore, the through current seems to always flow during the skew time Tskew. If the skew time is long, the internal voltage Vint may drop and the operation speed may fall as a consequence, and in the worst case cause MALFUNCTION.
As a solution to the above shortcoming, the capacitance of the capacitor 92 may be increased to provide a longer allowable skew time. But, the capacitance of the capacitor 92 is limited and it is not possible to match the increased skew time with that permitted by a device with the 5-V supply voltage Vcc or 3.3-V supply voltage Vcc which allows for an unlimited length of skew time from the viewpoint of the specifications. Moreover, this scheme undesirably increases the occupying area of the capacitor 92.